1. Field of the Invention
The present invention relates to a plasma display apparatus, and more particularly, to a plasma display apparatus and a driving method of the same, for preventing an erroneous discharge, a mistaken discharge, and an abnormal discharge, increasing a dark room contrast, for increasing an operation margin, and for differently embodying application time points of pulses applied in an address period and a sustain period.
2. Description of the Background Art
In a conventioal plasma display panel, one unit cell is provided at a space between barrier ribs formed between a front panel and a rear panel. A main discharge gas such as neon (Ne), helium (He) or a mixture (He+Ne) of neon and helium and an inert gas containing a small amount of xenon (Xe) fill each cell. When a discharge occurs using a high frequency voltage, the inert gas generates vacuum ultraviolet rays and phosphors provided between the barrier ribs are emitted, thereby realizing an image. The plasma display panel is considered as one of the next generation display devices due to its thin profile and light weigh construction.
FIG. 1 illustrates a structure of a conventional plasma display panel.
As shown in FIG. 1, a plasma display panel includes a front panel 100 and a rear panel 110. The front panel 100 has a plurality of sustain electrode pairs arranged with a scan electrode 102 and a sustain electrode 103 each paired and formed on a front glass 101, which is a display surface for displaying the image thereon. The rear panel 110 has a plurality of address electrodes 113 arranged to intersect with the plurality of sustain electrode pairs on a rear glass 111, which is spaced apart in parallel with and sealed to the front panel 100.
The front panel 100 includes the paired scan electrode 102 and the paired sustain electrode 103 for performing a mutual discharge in one pixel and sustaining an emission of light, that is, the paired scan electrode 102 and the paired sustain electrode 103 each having a transparent electrode (a) formed of indium-tin-oxide (ITO) and a bus electrode (b) formed of metal. The scan electrode 102 and the sustain electrode 103 are covered with at least one dielectric layer 104, which controls a discharge current and insulates the paired electrodes. A protective layer 105 is formed of oxide magnesium (MgO) on the dielectric layer 104 to facilitate a discharge.
The rear panel 110 includes stripe-type (or well-type) barrier ribs 112 for forming a plurality of discharge spaces (that is, discharge cells) that are arranged in parallel. The rear panel 110 includes a plurality of address electrodes 113 arranged in parallel with the barrier ribs 112 and performing an address discharge and generating the vacuum ultraviolet rays. Red (R), green (G) and blue (B) phosphors 114 emit visible rays for displaying the image in the address discharge and are coated over an upper surface of the rear panel 110. Lower dielectric layer 115 for protecting the address electrode 113 is formed between the address electrode 113 and the phosphor 114.
In the above constructed plasma display panel, electrodes are arranged in a matrix form, and this will be described with reference to FIG. 2 below.
FIG. 2 illustrates an arrangement structure of the electrodes formed on the conventional plasma display panel.
Referring to FIG. 2, the scan electrodes (Y1 to Yn) are formed to be in parallel with the sustain electrodes (Z1 to Zn) on the plasma display panel 200, and the address electrodes (X1 to Xm) are formed to intersect with the scan electrodes (Y1 to Yn) and the sustain electrodes (Z1 to Zn).
The discharge cells are formed at intersections of the scan electrodes (Y1 to Yn), the sustain electrodes (Z1 to Zn), and the address electrodes (X1 to Xm). Accordingly, the discharge cell is formed in a matrix form on the plasma display panel.
Driving circuits for supplying a predetermined pulse are attached to the plasma display panel having the above arranged electrodes, thereby constructing the plasma display apparatus.
The method for embodying the image gray level in the plasma display apparatus is illustrated in FIG. 3 below.
FIG. 3 illustrates the method for expressing the gray level of the image in the conventional plasma display apparatus.
As shown in FIG. 3, in the conventional method for expressing the image gray level in the plasma display apparatus, one frame is divided into several subfields, each subfield having a different number of emissions. Each subfield is divided into a reset period (RPD) for initializing all cells, an address period (APD) for selecting the discharge cell, and a sustain period (SPD) for expressing the gray level depending on the number of discharges. For example, when the image is displayed in 256 gray levels, as shown in FIG. 2, a frame period (16.67 ms) corresponding to a 1/60 second is divided into eight subfields (SF1 to SF8), and each of the eight subfields (SF1 to SF8) is divided into the reset period, the address period, and the sustain period.
Each subfield has the same period of reset period and the address period. The address discharge for selecting the cell to be discharged is generated by a voltage difference between the address electrode and the scan electrode being the transparent electrode. The sustain period is increased in a ratio of 2n (n=0, 1, 2, 3, 4, 5, 6, 7) for each subfield. Since the sustain period is different for each subfield as described above, the sustain period of each subfield (that is, the number of sustain discharges) is controlled, thereby expressing the image gray level.
FIG. 4 is a waveform diagram illustrating an example of the driving waveform of the conventional plasma display panel. FIGS. 5A to 5E are stepwise diagrams illustrating a distribution of the wall charges within the discharge cell varied by the driving waveform of FIG. 4.
The driving waveform of FIG. 4 will be described with reference to the wall charge distributions of FIGS. 5A to 5E.
Referring to FIG. 4, each of the subfields (SFn−1and SFn) includes the reset period (RP) for initializing the discharge cells 1 of a whole screen, the address period (AP) for selecting the discharge cell, the sustain period (SP) for sustaining discharge of the selected discharge cell 1, and the erasure period (EP) for erasing the wall charges within the discharge cell 1.
In the erasure period (EP) of the (n−1)th subfield (SFn−1), an erasure ramp waveform (ERR) is applied to the sustain electrodes (Z). During the erasure period (EP), 0V is applied to the scan electrodes (Y) and the address electrodes (X). The erasure ramp waveform (ERR) is a positive ramp waveform having a voltage that gradually increases from 0V to a positive sustain voltage (Vs). During the erasure ramp waveform (ERR), an erasure discharge is generated between the scan electrode (Y) and the sustain electrode (Z) within on-cells. During the erasure discharge, the wall charges are erased within on-cells. As a result, each discharge cell 1 has the wall charge distribution soon after the erasure period (EP) as in FIG. 5A.
In a setup period (SU) of the reset period (RP) where the nth subfield (SFn) begins, the positive ramp waveform (PR) is applied to all scan electrodes (Y), and 0V is applied to the sustain electrodes (Z) and the address electrodes (X). During the positive ramp waveform (PR) of the setup period (SU), voltages of the scan electrodes (Y) gradually increase from the positive sustain voltage (Vs) to a reset voltage (Vr) more than the positive sustain voltage (Vs). During the positive ramp waveform (PR), a dark discharge is generated between the scan electrodes (Y) and the address electrodes (X) within the discharge cells of the entire screen and concurrently, the dark discharge is generated between the scan electrodes (Y) and the sustain electrodes (Z). As a result of the dark discharge, soon after the setup period (SU), as shown in FIG. 5B, positive wall charges remain on the address electrodes (X) and the sustain electrodes (Z), and negative wall charges remain on the scan electrode (Y). In the setup period (SU), while the dark discharge is generated, gap voltages (Vg) between the scan electrodes (Y) and the sustain electrodes (Z) and gap voltages between the scan electrodes (Y) and the address electrodes (X) are initialized to a voltage close to a discharge firing voltage (Vf) that is capable of generating a discharge.
Subsequent to the setup period (SU), in a setdown period (SD) of the reset period (RP), a negative ramp waveform (NR) is applied to the scan electrodes (Y). At the same time, the positive sustain voltages (Vs) are applied to the sustain electrodes (Z) and 0V is applied to the address electrodes (X). During the negative ramp waveform (NR), voltages of the scan electrodes (Y) gradually decrease from the positive sustain voltage (Vs) to the negative erasure voltage (Ve). During the negative ramp waveform (NR), the dark discharge is generated between the scan electrodes (Y) and the address electrodes (X) within the discharge cell of the whole screen and concurrently, the dark discharge is generated even between the scan electrodes (Y) and the sustain electrodes (Z). As a result of the dark discharge of the setdown period (SD), the wall charge distribution within each discharge cell 1 is changed to have an optimal condition for address dischrgae as in FIG. 5C. At this time, excessive wall charges unnecessary for the address discharge are erased and a predetermined amount of wall charges remain on the scan electrodes (Y) and the address electrodes (X) within each discharge cell 1. The wall charges on the sustain electrodes (Z) are converted from a positive polarity to a negative polarity while the negative wall charges are moved from the scan electrodes (Y) and accumulated. In the setdown period (SD) of the reset period (RP), while the dark discharge is generated, the gap voltages between the scan electrodes (Y) and the sustain electrodes (Z), and the gap voltages between the scan electrodes (Y) and the address electrodes (X) are close to the discharge firing voltage (Vf).
In the address period (AP), negative scan pulses (−SCNP) are sequentially applied to the scan electrodes (Y) and at the same time, the scan electrodes (Y) are synchronized with the negative scan pulses (−SCNP), so that the positive data pulses (DP) are applied to the address electrodes (X). A scan pulse (−SCNP) voltage is a scan voltage that decreases from 0V or a negative scan bias voltage (Vyb) close to 0V to a negative scan voltage (−Vy). A data pulse voltage (DP) is the positive data voltage (Va). During the address period (AP), a positive Z bias voltage (Vzb) that is less than the positive sustain voltage (Vs) is supplied to the sustain electrodes (Z). Where the gap voltage is maintained at a level close to the discharge firing voltage (Vf) soon after the reset period (RP), the gap voltage between the scan electrodes (Y) and the address electrodes (X) exceeds the discharge firing voltage (Vf) while the address discharge is generated between the electrodes (X and Y) within the on-cells to which the scan voltage (Vsc) and the data voltage (Va) are applied. A primary address discharge between the scan electrodes (Y) and the address electrodes (X) generates priming charged particles within the discharge cell and, as in FIG. 5D, induces a secondary discharge between the scan electrodes (Y) and the sustain electrodes (Z). The wall charge distribution within the on-cells generating the address discharge is as shown in FIG. 5E.
The wall charge distribution within off-cells not generating the address discharge substantially maintains a state shown in FIG. 5C.
In the sustain period (SP), the sustain pulses (SUSP) of the positive sustain voltage (Vs) are alternately applied to the scan electrodes (Y) and the sustain electrodes (Z). In the on-cells selected by the address discharge, the sustain discharge is generated between the scan electrodes (Y) and the sustain electrodes (Z) for each sustain pulse (SUSP) with the assistance of the wall charge distribution of FIG. 5E. In the off-cells, the discharge is not generated during the sustain period. This is because the wall charge distribution of the off-cells is maintained in a state as shown in FIG. 5C so that, when an initial sustain voltage (Vs) is applied to the scan electrodes (Y), the gap voltage between the scan electrodes (Y) and the sustain electrodes (Z) cannot exceed the discharge firing voltage (Vf).
However, in the conventional plasma display apparatus, there is a drawback in that, during the erasure period (EP) of the (n−1)th subfield (SFn−1) and the reset period (RP) of the nth subfield (SFn), the discharge is generated several times to initialize the discharge cells 1 and to control the wall charges, thereby reducing the darkroom contrast and reducing a contrast ratio. Table 1 below is an arrangement of a discharge type and the number of discharges generated in the erasure period (EP) and the reset period (RP) of the previous subfield (SFn−1) in the conventional plasma display apparatus.
TABLE 1OperationperiodRP of SFnCell stateEP of SFn-1SUSDOn-cell turnedOpposite discharge (Y-X)X◯◯on in SFn-1Surface discharge (Y-Z)◯◯◯Off-cell turnedOpposite discharge (Y-X)X◯◯off in SFn-1Surface discharge (Y-Z)X◯◯
As shown in Table 1, in the on-cells turned on in the (n−1)th subfield (SFn−1), during the erasure period (EP) and the reset period (RP), a surface discharge between the scan electrodes (Y) and the sustain electrodes (Z) is generated three times, and an opposite discharge between the scan electrodes and the address electrodes is generated two times. In the off-cells turned off in the previous subfield (SFn), during the erasure period (EP) and the reset period (RP), the surface discharge between the scan electrodes (Y) and the sustain electrodes (Z) is generated two times, and an opposite discharge between the scan electrodes (Y) and the address electrodes (X) is generated two times.
The discharges generated several times during the erasure period and the reset period increase the emissions in the erasure period and the reset period when the amount of emissions should be minimized if possible in consideration of a contrast characteristic, thereby causing a reduction of the darkroom contrast value. In particular, the surface discharge between the scan electrodes (Y) and the sustain electrodes (Z) provides a significant light emission in comparison to the opposite discharge between the scan electrodes (Y) and the address electrodes (X) and therefore, has a negative influence on the darkroom contrast in comparison with the opposite discharge.
In the conventional plasma display apparatus, in the erasure period (EP) of the (n−1)th subfield (SFn−1), the wall charges are not completely erased and therefore, where the negative wall charges are excessively accumulated on the scan electrodes (Y), the dark discharge is not generated in the setup period (SU) of the nth subfield (SFn). If the dark discharge is not normally generated in the setup period (SU), the discharge cells are not initialized. To generate the discharge in the setup period, the reset voltage (Vr) must be increased. If the dark discharge is not generated in the setup period (SU), the discharge cell is not in the optimal address condition soon after the reset period, thereby causing an abnormal discharge or an erroneous discharge. Where the positive wall charges are excessively accumulated on the scan electrodes (Y) soon after the erasure period (EP) of the (n−1)th subfield (SFn−1), in the setup period (SU) of the nth subfield (SFn), when the positive sustain voltage (Vs) being an initiation voltage of the positive ramp waveform (PR) is applied to the scan electrodes (Y), an excessive discharge is generated, thereby not uniformly initializing all of the cells.
FIG. 6 illustrates variations of an external voltage applied between the scan electrode and the sustain electrode and the gap voltage within the discharge cell in the setup period when the plasma display panel is driven by the driving waveform of FIG. 4.
FIG. 6 illustrates the external application voltage (Vyz) between the scan electrodes (Y) and the sustain electrodes (Z) and the gap voltage (Vg) within the discharge cell in the setup period (SU). In FIG. 6, the external application voltage indicated by a solid line is an external voltage applied to each of the scan electrodes (Y) and the sustain electrodes (Z) and is about equal to the voltage of the positive ramp waveform (PR) since 0V is applied to the sustain electrodes (Z). In FIG. 6, dotted lines {circle around (1)}, {circle around (2)} and {circle around (3)} denote the gap voltages (Vg) provided for a discharge gas by the wall charges within the discharge cell. The gap voltage (Vg) varies as shown by the dotted lines {circle around (1)}, {circle around (2)} and {circle around (3)} since the number of wall charges within the discharge cell varies by an amount depending on whether or not the discharge is generated in the previous subfield. The relationship between the external application voltage (Vyz) between the scan electrodes (Y) and the sustain electrodes (Z) and the gap voltage (Vg) provided for the discharge gas within the discharge cell is expressed in Equation 1 below.Vyz=Vg+Vw   [Equation 1]
In FIG. 6, the gap voltage (Vg) of the dotted line {circle around (1)} represents the wall charges that are sufficiently erased within the discharge cell, thereby the wall charges are sufficiently reduced. The gap voltage (Vg) increases in proportion to the external application voltage (Vyz). When the gap voltage (Vg) equals the discharge firing voltage (Vf), the dark discharge is generated. Due to this dark discharge, the gap voltage within the discharge cells is initialized to the discharge firing voltage (Vf).
In FIG. 6, the gap voltage (Vg) of the dotted line {circle around (2)} represents a strong discharge generated during the erasure period of the (n−1)th subfield (SFn−1). The gap voltage (Vg) inverts the polarities of the wall charges in the wall charge distribution within the discharge cells. Soon after the erasure period (EP), the polarities of the wall charges accumulated on the scan electrodes (Y) are converted into the positive polarities due to the strong discharge. This occurs because there is low uniformity among the discharge cells or there is a variation of a slope of the erasure ramp waveform (ERR) depending on temperature variation where there is a large sized PDP. The initial gap voltage (Vg) increases too much as shown in the dotted line {circle around (2)} of FIG. 6 and therefore, in the setup period (SU), the positive sustain voltage (Vs) is applied to the scan electrodes (Y) and at the same time, the gap voltage (Vg) exceeds the discharge firing voltage (Vf), thereby generating the strong discharge. Due to this strong discharge, in the setup period (SU) and the setdown period (SD), the discharge cells are not initialized in the wall charge distribution of the optimal address condition, that is, in the wall charge distribution of FIG. 4C. Therefore, the address discharge can be generated in the off-cells that need to be turned off. In other words, when the erasure discharge is strongly generated in the erasure period prior to the reset period, an erroneous discharge can occur.
In FIG. 6, during the erasure period (EP) of the (n−1)th subfield (SFn−1), the gap voltage (Vg) of the dotted line {circle around (3)} represents the erasure discharge that is very weak or not generated, which maintains the wall charge distribution that is formed as a result of the sustain discharge generated just before the erasure discharge within the discharge cells. In a detailed description, as shown in FIG. 3, the last sustain discharge is generated when the sustain pulse (SUSP) is applied to the scan electrodes (Y). As a result of the last sustain discharge, the negative wall charges remain on the scan electrodes (Y) and the positive wall charges remain on the sustain electrodes (Z). However, such wall charges need to be erased to perform a normal initialization in a next subfield but when the erasure discharge is very weak or is not generated, the polarity does not change. A reason why the erasure discharge is very weak or is not generated is that in the PDP, the discharge cells are non-uniform in uniformity or the erasure ramp waveform (ERR) is varied in slope depending on the temperature variation. The initial gap voltage (Vg) is too low to have the negative polarity as shown in the dotted line {circle around (3)} of FIG. 6 and therefore, even though the positive ramp waveform (PR) increases up to the reset voltage (Vr) in the setup period, the gap voltage (Vg) within the discharge cells does not equal the discharge firing voltage (Vf). Therefore, the dark discharge is not generated in the setup period (SU) and the setdown period (SD). As a result, where the erasure discharge is very weak or is not generated in the erasure period prior to the reset period, the initialization is not performed properly, thereby causing an erroneous discharge or an abnormal discharge.
In the dotted line {circle around (2)} of FIG. 6, the relationship between the gap voltage (Vg) and the discharge firing voltage (Vf) is expressed as shown in Equation 2, and shown in the dotted line {circle around (3)} of FIG. 6, the relationship between the gap voltage (Vg) and the discharge firing voltage (Vf) is expressed as in Equation 3:Vgini+Vs>Vf  [Equation 2]Vgini+Vr<Vf  [Equation 3]where, Vgini represents initial gap voltage just before the setup period (SU) is initiated as shown in FIG. 6.
A gap voltage condition (or wall charge condition) for performing the normal initialization in the erasure period (EP) and the reset period (RP) considering the above drawbacks is expressed in the following Equation 4 that satisfys Equations 2 and 3:Vf−Vr<Vgini<Vf−Vs  [Equation 4]
If the initial gap voltage (Vgini) does not satisfy the condition of the Equation 4 before the setup period (SU), the conventional plasma display apparatus can cause an erroneous discharge, a mistaken discharge, or an abnormal discharge and a decrease in the operational margin. In other words, in the conventional plasma display apparatus, to secure the operational reliability and the operation margin, an erasure operation in the erasure period (EP) should be normally performed but, as aforementioned, can be abnormally performed depending on the uniformity of the discharge cell or the use temperature of the PDP.
In the conventional plasma display apparatus, there is a drawback in that, due to excessive space charges apprearing in a high temperature environment and the active motion of the space charges, the wall charge distribution becomes unstable, thereby causing the erroneous discharge, the misdischarge, or the abnormal discharge and therefore, the operational margin decreases. This will be described in detail with reference to FIGS. 7A to 7C.
FIGS. 7A to 7C illustrate the space charges and the motion of the space charges when the plasma display panel is driven in a high temperature environment by the driving waveform of FIG. 4.
In a high temperature environment, the quantity and the momentum of the space charges generated in a discharge are increased more than in a room temperature or in a low temperature. Accordingly, in the sustain discharge of the (n−1)th subfield (SFn−1), many space charges are generated, and soon after the setup period (SU) of the nth subfield (SFn), as shown in FIG. 7A, many space charges 300 that are in active motion remain within a discharge space.
As in FIG. 7A, where the space charges 300 in active motion exist within the discharge space, during the address period, the data voltage (Va) is applied to the address electrode (X), and the scan voltage (−Vy) is applied to the scan electrode (Y). As shown in FIG. 7B, as a result of the setup discharge of the setup period (SU), the positive space charges 300 are recombined with the negative wall charges accumulated on the scan electrode (Y), and the negative space charges 300 are recombined with the positive wall charges accumulated on the address electrode (Y) as a result of the setup discharge.
As shown in FIG. 7C, the negative wall charges on the scan electrode (Y) and the positive wall charges on the address electrode (X) formed by the setup discharge are erased so that, though the data voltage (Va) and the scan voltage (−Vy) are applied to the address electrode (X) and the scan electrode (Y), the gap voltage (Vg) does not equal the discharge firing voltage (Vf). Therefore, the address discharge is not generated. Accordingly, there is a drawback in that, when the driving waveform of FIG. 4 is applied to a PDP used in a high temperature environment, mistaken writing of the on-cells will occur frequently.
FIG. 8 illustrates another example of the driving waveform according to a conventional driving method of the plasma display apparatus.
As shown in FIG. 8, in the plasma display apparatus, all of the cells are driven with the subfield divided into the reset period for initializing all cells, the address period for selecting the discharge cell, the sustain period for sustaining the discharge of the selected cell, and the erasure period for erasing the wall charges within the discharged cell.
In the setup period of the reset period, the ramp-up waveform (ramp-up) is concurrently applied to all scan electrodes (Y). During this ramp-up waveform, a weak dark discharge is generated within the discharge cells of the whole screen. Due to this setup discharge, the positive wall charges are accumulated on the address electrode (X) and the sustain electrode (Z) and the negative wall charges are accumulated on the scan electrode (Y).
In the setdown period, the ramp-up waveform is applied and then, a ramp-down waveform which falls from a positive voltage less than a peak voltage of the ramp-up waveform to a specific voltage level less than a ground level(GND) generates a weak erasure discharge within the cells, thereby sufficiently erasing the wall charges excessively formed in the scan electrode (Y). Due to setdown discharge, there are enough wall charges to generate a stable address discharge, which will uniformly remain within the cells.
In the address period, the negative scan pulses are sequentially applied to the scan electrodes (Y) and at the same time, the scan electrodes (Y) are synchronized with the scan pulses, thereby applying the positive data pulse to the address electrode (X). As a voltage difference between the scan pulse and the data pulse is added to a wall voltage generated in the reset period, the address discharge is generated within the discharge cell to which the data pulse is applied. The wall charges are formed within the cells selected by the address discharges, so that the discharge is generated when the sustain voltage (Vs) is applied. The positive voltage (Vz) is supplied to the sustain electrode so that, during the setdown period and the address period, the voltage difference with the scan electrode decreases, thereby preventing an erroneous discharge with the scan electrode.
In the sustain period, the sustain pulse (Sus) is alternately applied to the scan electrode (Y) and the sustain electrode (Z). In the cell selected by the address discharge, while the wall voltage within the cell is added to the sustain pulse, the sustain discharge, that is, the display discharge is generated between the scan electrode (Y) and the sustain electrode (Z) whenever the sustain pulse is applied.
After the completion of the sustain discharge, the erasure period can also be included. In this erasure period, a voltage of an erasure ramp waveform (ramp-ers) having a narrow pulsewidth and a low voltage level is supplied to the sustain electrode (Z), thereby erasing the remaining wall charges within the cells of the whole screen.
In the plasma display apparatus driven using the driving waveform, in the address period, the application time point of the scan pulse applied to the scan electrode (Y) is the same as application time points of the data pulses applied to the address electrodes (X1 to Xn). In the conventional driving method, the application time points of the scan pulse and the data pulse in the address period will be described with reference to FIG. 9 below.
FIG. 9 illustrates the application time point of the pulse applied in the address period in the conventional driving method of the plasma display apparatus.
As shown in FIG. 9, in the driving method of the conventional plasma display apparatus, in the address period, all data pulses are applied to the address electrodes (X1 to Xn) at the same time (ts) as the scan pulses are applied to the scan electrode (Y). If the data pulse and the scan pulse are applied to the address electrodes (X1 to Xn) and the scan electrode (Y) at the same time point, respectively, noise is generated in a waveform applied to the scan electrode (Y) and a waveform applied to the sustain electrode (Z). An example of the noise generated when the data pulse and the scan pulse are applied to the address electrodes (X1 to Xn) and the scan electrode at the same time point, respectively will be described with reference to FIG. 10 below.
FIG. 10 illustrates the generation of noise resulting from the pulses applied in the address period in the conventional driving method of the plasma display apparatus.
As shown in FIG. 10, in the conventional driving method of the plasma display apparatus, if the data pulse and the scan pulse are applied to the address electrodes (X1 to Xn) and the scan electrode (Y) in the address period, respectively, noise is generated in the waveform applied to the scan electrode (Y) and the sustain electrode (Z). The noise is generated due to coupling through the capacitance of a PDP. At a time point when the data pulse rises abruptly, a rising noise is generated in the waveform applied to the scan electrode (Y) and the sustain electrode (Z), and at a time point when the data pulse falls abruptly, a falling noise is generated in the waveform applied to the scan electrode (Y) and the sustain electrode (Z).
As mentioned above, there is a drawback in that the scan pulse applied to the scan electrode (Y) and concurrently, the data pulse applied to the address electrode (X) result in noise being generated in the waveform applied to the scan electrode (Y) and the sustain electrode (Z) which then causes an unstable address discharge to be generated in the address period, thereby reducing the driving efficiency of the plasma display panel.
In the conventional plasma display apparatus driven using the driving waveform, the erroneous discharge is generally caused by a temperature around the panel that is high. The erroneous discharge caused by the temperature will be described with reference to FIG. 11 below.
FIG. 11 illustrates the erroneous discharge depending on the temperature in the plasma display apparatus operating by the driving waveform based on the conventional driving method.
Referring to FIG. 11, in the plasma display apparatus operating by the driving waveform according to the conventional driving method, when the temperature around the panel is relatively high, a recombination ratio of the space charges 401 to the wall charges 400 within the discharge cell is increased, and an absolute amount of the wall charges participating in the discharge decreases, thereby causing the erroneous discharge. The space charges 401 exist in the space within the discharge cell, and do not take part in the discharge unlike the wall charges 400.
For example, the recombination ratio of the space charges 401 to the wall charges 400 increases in the address period and the amount of the wall charges 400 taking part in the address discharge decreases, thereby destabilizing the address discharge. As addressing is performed later, a time for recombining the space charges 401 and the wall charges 400 is sufficiently secured. Therefore, the address discharge is more unstable. Accordingly, a high temperature erroneous discharge occurs, thereby turning-off the turned-on discharge cell of the address period, in the sustain period.
Where the temperature around the panel is relatively high, upon generation of the sustain discharge in the sustain period, the space charges 401 are speeded up in the discharge and accordingly, the recombination ratio of the space charges 401 to the wall charges 400 increases. Accordingly, there is a drawback in that after any one sustain discharge, the recombination of the space charges 401 and the wall charges 400 causes the wall charges 400 participating in the sustain discharge to decrease in amount, thereby causing the high temperature erroneous discharge that does not generate a next sustain discharge.